Verilog Signed, Unsigned Arithmetic Note

In Verilog and SystemVerilog, if you mix unsigned and signed operands, unsigned arithmetic will be used. So, as both operands are signed, signed arithmetic will be used. (Whether the result is unsigned or signed is irrelevant.)

For example following code, simulation result shows p is a positive number 0x0080, which is not right. After use $signed system task to convert unsigned operand to be signed, the result is right to be 0x3f80, which has signed extended as expected. 

1 module mult_test();
2
3 reg signed [7:0] a = 8’h80;
4 reg [4:0] b = 5’h01;
5 reg signed [13:0] p,q;
6
7 always @(*) begin
8     p = a*b;
9     q = a*$signed({1’b0,b});
10 end
11
12 always @(*) begin
13     $display(“a=0x%h, b=0x%h, p=0x%h, q=0x%h”, a, b, p, q);
14 end
15
16 endmodule // mult_test();

“a=0x80, b=0x01, p=0x0080, q=0x3f80”